Statistical Estimation of Leakage Power Dissipation in Nano-Scale CMOS Digital Circuits using Generalized Extreme Value Distribution
نویسندگان
چکیده
In this paper, we present an accurate approach for the estimation of statistical distribution of leakage power consumption in the presence of process variations in nano-scale CMOS technologies. The technique, which is additive with respect to the individual gate leakage values, employs Generalized Extreme Value (GEV) distribution. Compared to the previous methods based on (two-parameter) lognormal distribution, this method uses GEV distribution with three parameters to increase the accuracy. Using the suggested distribution, the leakage yield of circuits may be modeled. The accuracy of the approach is studied by comparing its results with those of a previous technique and HSPICE-based Monte Carlo simulations on ISCAS85 benchmark circuits for 45 nm CMOS technology. The comparison reveals a higher accuracy for the proposed approach. The proposed distribution does not add to the complexity and cost of simulations compared to the case of the lognormal distribution.
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